The present invention relates to solid-state image sensors, specifically to Complementary Metal-Oxide-Semiconductor (CMOS) image sensors that have very small pixel sizes. In more particular the present invention relates to pixels that use only two transistors (2T) and a diode for the reset and addressing instead of the typical reset and addressing transistors. Further more the diode can be built vertically on top of the silicon substrate and have a very small size in order not to occupy the valuable pixel area. A Source Follower (SF) MOS transistor for sensing charge has been replaced in this pixel by a depletion mode n-channel Junction gate Field-Effect Transistor (JFET), which gives the pixel very low noise performance. The described pixel is still capable of standard low noise correlated double sampling (CDS) operation as is typically used with 4T pixel architectures. This further contributes to the pixel high performance with high conversion gain and maximum optical symmetry.
The typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of integration cycle collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In typical CMOS image sensors the charge to voltage conversion is accomplished directly in the pixels themselves and the converted analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can also be converted on-chip to a digital equivalent before reaching the chip output. The pixels have incorporated in them a buffer amplifier, typically a source follower, which drives sense lines that are connected to the pixels by suitable addressing transistors. After charge to voltage conversion is completed and the resulting signal is transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In pixels that are using Floating Diffusion (FD) node as a charge detection node, the reset is accomplished by turning on the reset transistor that momentarily conductively connects the FD node to a voltage reference. This step removes charge collected on the FD node; however, it generates kTC-reset noise as is well known in the art. The kTC noise has to be removed from the signal by the CDS signal processing technique in order to achieve desired low noise performance. The typical CMOS sensors that utilize the CDS concept need to have four transistors (4T) in the pixel. An example of the 4T pixel circuit can be found in the U.S. Pat. No. 5,904,493 to Guidash.
Recently a new pixel operating technique has been developed in the literature and in many products. The pixel having three transistors (3T) where the addressing transistor is eliminated is proposed. In the 3T pixel, the pixel addressing is accomplished by the Source Follower (SF) transistor itself through applying a suitable bias on the FD nodes that are not selected. The latest description of this concept can be found for example in the: ISSCC 2007 Digest of Technical Papers, “A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders” pp. 510˜511, by Hidekazu Takahashi et al. Eliminating the addressing transistor from the pixel saves the valuable pixel area and also eliminates one control wire that was needed for controlling the addressing transistor gate.
FIG. 1 is a schematic circuit diagram illustrating a conventional 3T pixel. The 3T pixel includes a pinned photo-diode PD and three MOS transistors MT1 to MT3. The photodiode PD is coupled through the first MOS transistor MT1, which is for transferring charge, to a FD node 101. The second MOS transistor MT2, which is a Source Follower (SF) transistor for sensing charge, has its gate connected to the FD node 101, the drain connected to VDD node 102 and the source connected to an output column bus 103. The VDD node 102 is connected to the VDD column bus 104 that is further connected to the drain switch SW. The FD node 101 is reset to VDD node 102 by the third MOS transistor MT3, i.e., a reset transistor. The gate of the third MOS transistor MT3 is controlled by a row bus line 110 and the gate of the second MOS transistor M1 is controlled by a second row bus line 111.
As photons 120 impinge on the photodiode PD, electron charge is generated there. After completion of charge integration the FD node 101 is reset and all charge from the photodiode PD is transferred on the FD node 101. This changes the FD voltage from the original reset level to a new signal level. Both levels; the reset level and signal level on the FD node 101 are then sensed by the second MOS transistor MT2 and both levels are transferred onto the output column bus 103 and further into column signal processing circuits for subtraction and additional processing. The subtraction of the reset level from the signal level is called Correlated Double Sampling (CDS), which removes the kTC noise and the transistor threshold non-uniformities from the signal. In order to prevent interference from signals that are generated on second MOS transistors of pixels in the remaining rows that are not addressed and are connected to the same column, the FD nodes of these pixels are set low. This turns first MOS transistors, i.e., the SF transistors, of these pixels off, since the SF transistor of the selected pixel is biased high.
The advantage of the 3T pixel circuit is that fewer transistors occupy less pixel area and the elimination of the addressing transistor eliminates the gate addressing line, lowers the pixel output impedance and eliminates noise generated in that transistor. However, the three transistors still occupy a significant amount of the valuable active pixel area, which is a problem for further reduction of pixel size and thus for lowering the cost of the CMOS image sensors. This disadvantage is often times compensated by sharing the pixel circuit with several photo diodes. However, the circuit sharing has also its disadvantages. In such circuits the FD node capacitance is increased, which reduces the pixel sensitivity, and interconnection lines also occupy the valuable pixel area. Other disadvantages of the sharing concept are slightly asymmetrical layout and electrical functions that result is some asymmetrical optical as well as electrical cross talk problems. It is therefore desirable to design a pixel that have very small size to begin with and that do not sharing of the circuits excessively.